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Alif Semiconductor /AE302F40C1537LE_CM55_HP_View /ADC120 /ADC_SAMPLE_WIDTH

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Interpret as ADC_SAMPLE_WIDTH

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31282724232019161512118743000000000000000000000000000000000000000000SAMPLE_WIDTH0 (SAMPLE_HOLD)SAMPLE_HOLD

Description

ADC Sampling Signal Duration Register

Fields

SAMPLE_WIDTH

Duration of the Sample signal to ADC analog frond-end in PCLK clocks. Valid values are 2 to 32.
SAMPLE_HOLD

Used in ADC24. If 1, the Sample signal is continuously active while gathering data.

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data